UltraTemp™

UltraTemp™ Technology Overview:

HTI has developed and patented the UltraTemp™ technology, an exciting method for passively cooling hot components on printed circuit boards. Heat can leave hot components on PCBs through two avenues. First, heat can proceed through the IC component top and either radiate out to surroundings or convect into the ambient air. Heatsinks can aid this process if space permits. The second path involves the PCB upon which the IC component sits. A significant portion of heat generated by the IC moves downward into the board through leads, ball grids, or whatever electrical connection is present. This PCB portion can be as much as three quarters of the total component heat load, particularly in low or zero velocity ambient airflows. The figure below shows these two distinct thermal pathways leading from the IC hot die out into the ambient environment.

UltraTemp™ Boards increase the amount of heat that leaves the IC component die through the PCB. Our patented methods allow us to create boards with significant quantities of aluminum in the center. This aluminum greatly increases the capacity of the PCB to remove heat. The average thermal conductivity of an UltraTemp™ board can be increased to more than six times that of an ordinary PCB of the same thickness. This means far more heat can leave the IC package into the PCB into the air.

The figure below shows an example of one of our UltraTemp™ Boards. It looks like an ordinary PCB. It had 5mil lines, 5mil spacings and 12mil thermal vias. The center layer of the board is .031 inch of aluminum.

UltraTemp™ Technical and Process Information:

HTI's patent pending printed circuit substrate material consists of a rigid insulated aluminum core that is laminated with copper foil using a high temperature thermoplastic resin. The high thermal conductivity core is insulated with a precisely controlled layer of anodically grown aluminum oxide. The fluoropolymer resin is pressure impregnated into the columnar structure of the aluminum oxide insulation materials and the dendritic structure of the copper foil for minimum thickness and improved thermal conductance. Copper plated through holed vias provides an excellent thermal connection to the core material. Here all through holed vias are electrically insulated but thermally connected to the core.

Use of the core material allows for direct silicon die attaches with minimal mechanical stress due to thermal mismatches.

Junction temperature rise for high power dissipation chips can be reduced by a factor or three or more in the same airflow and temperature without added heatsinks in many applications. The allowable ambient temperature can increase for the same product design without compromising the junction temperature with this product. Alternatively, the same junction temperature can be maintained for power dissipation increases of a factor of three or more for the same conditions.

There is limited data available on the actual performance and long-term reliability of the product. Test samples showed excellent conductivity and did not degrade after 125 thermal cycles followed by 240 hours of pressure pot testing

Material Properties:
ISOLATION THICKNESS			MILS	2.0
(Typical)
DC HI-POT BREAKDOWN TEST			KV	2.5
(minimum)
EST. THERMAL CONDUCTIVITY			W/M deg C	162.6
(In Plane, Aluminum)
EST. THERMAL CONDUCTIVITY			W/M deg C	190.3
(In Plane, SiC/Al)
PEEL STRENGTH			Lbs/in	10
PULL STRENGTH			Lbs/in.2	2500

Processing: The laminated material can be processed under a variety of conditions.
Board blanks are supplied with edges sealed, so that no exposed aluminum is present during copper etching procedures. The material is table to all known copper etching methods. After routering exposed aluminum edges will be present.
Additional layers are added using conventional Kapton/copper flex-circuit materials. These are laminated to the core sandwich with standard thermoplastic polyester or thermosetting acrylic adhesives.
The fluoropolymer thermoplastic adhesive melts only above 310 C, so that tracks are stable at soldering temperatures for wave-soldering, vapors-phase, oven and belt furnace operations. Soldering times and furnace temperatures may need adjustment due to increase thermal capacity of the material.
Through core vias must be pre-drilled at the factory as part of the core manufacturing process.

Cleaning Procedures: Cleaning procedures vary depending upon the severity of the contamination. The core metal and isolation system may show sensitivity to severe caustic solutions. The effect of bare aluminum edges exposed after routering should be considered when selecting cleaning methods. These may require subsequent treatment.
Computational fluid dynamics models of chip and printed circuit module performance are rapidly gaining widespread acceptance in the electronics industry.
A typical 10 watt chip was modeled using FLOTHERM, in a 20 deg C airstream at 200LFM airflow rate and mounted on a 6"x9" board made of various layer constructions. The chip package was 1.2" square and used a bare tungsten-copper heat spreader without external heatsink but also exposed to the airflow. The construction of the chip package assumes 200 pins and vias, which approximate several current high performance PGA and BGA designs.
Results were as follows:

Module Description:		Predicted Junction Temperature- deg C	Temperature Improvement
A) Conventional G-10		146
(2 signal layers)
B) Conventional G-10		95
(2 signal plus 2 pwr-gnd)
C) Conventional G-10		72
(6 signal plus 4 pwr-gnd)
D) UltraTemp™ Core		41.4	[A vs D](126/21.4)= 5.9X
(2 signal layers)
E) UltraTemp™ Core		41.4	[B vs E](75/21.1)= 3.6X
(2 signal plus 2 pwr-gnd)
F) UltraTemp™ Core		40.9	[C vs F](52.20.9)= 2.5X
(6 signal plus 4 pwr-gnd)

Test Results: Thermal cycling test and pressure pot test are two methods that have proven to give a good indication of a material's performance with respect to time and environment. These tests have been well established in the industry and are commonly used t compare material performance.
The laminated material has been subject to 5 cycles of liquid to liquid immersion from -75C to +100C, with dwell times at each temperature of 10 minutes. No failures occurred.